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W83196R-718
DDR/SDRAM BUFFER
W83196R - 718
Data Sheet Revision History
Pages
Dates
Versio n
Version On Web n.a.
Main Contents
1 2 3 4 5 6 7 8 9 10
n.a. n.a 02/July 1.0
All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0
1.0
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATI ONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such appli do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
cations
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Publication Release Date:July. 2002 Revision 1.0
W83196R_718
PRELIMINARY 1.0 GENERAL DESCRIPTION
The W83196R-718 is a 2.5V/3.3V Clock buffer. W83196R_718 can support 4 D.D.R. DRAM DIMMs or 3 standard SDRAM and 2 D.D.R. DRAM DIMMs. W83196R-718 can be incorporated with W83194BR-P4X or W83194BR-325. The W83196R_718 provides I2C serial bus interface to program the registers to enable or disable each clock outputs. The W83196R_718 accepts a reference clock as its input and runs on a 3.3V or 2.5V supply.
2.0
* * * * * * * *
PRODUCT FEATURES
One input to 24 outputs buffer Supports up to 4 D.D.R. DIMMs or 3 SDRAM DIMMs and 2 D.D.R. DIMMs One additional output for feedback Low Skew outputs (< 100ps)
Support s up to 200MHz D.D.R. SDRAM I C 2-Wire serial interface and supports Byte or Block Date RW
2
Power management pin for power down control 48-pin SSOP package
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY 3.0 PIN CONFIGURATION
FB_output Vdd3.3_2.5 Vss DDR0T_SDRAM0 DDR0C_SDRAM1 DDR1T_SDRAM2 DDR1C_SDRAM3 Vdd3.3_2.5 Vss DDR2T_SDRAM4 DDR2C_SDRAM5 Vdd3.3_2.5 Buffer_IN Vss DDR3T_SDRAM6 DDR3C_SDRAM7 Vdd3.3_2.5 Vss DDR4T_SDRAM8 DDR4C_SDRAM9 DDR5T_SDRAM10 DDR5C_SDRAM11 Vdd3.3_2.5 SDATA* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SEL_DDR* Vdd2.5 Vss DDR11T DDR11C DDR10T DDR10C Vdd2.5 Vss DDR9T DDR9C Vdd2.5 PD#* Vss DDR8T DDR8C Vdd2.5 Vss DDR7T DDR7C DDR6T DDR6C Vss SCLK*
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
*: Internal pull-up resistor 120K to Vdd3.3_2.5 #: Active low
Block Diagran
FB_OUT DDRT0_SDRAM0 DDRC0_SDRAM1 DDRT1_SDRAM2 DDRC1_SDRAM3 DDRT2_SDRAM4 DDRC2_SDRAM5 DDRT3_SDRAM6 DDRC3_SDRAM7 DDRT4_SDRAM8 DDRC4_SDRAM9 DDRT5_SDRAM10 DDRC5_SDRAM11 6 6 DDRT(11:6) DDRC(11:6)
BUF_IN
SCLK SDATA SEL_DDR* PD#* Control Logic
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY 4.0 PIN DESCRIPTION
IN - Input OUT - Output I/O - Bi-directional Pin # - Active Low *- Internal 120k pull-up
4.1 Pin Description
SYMBOL SEL_DDR PIN 48 I/O IN FUNCTION 1= DDR only mode 0=Standard SDRAM mode When SEL_DDR is pulled high. Pin 4,5,6,7,10,11,15, 16,19,20,21,22,27,28,29,30,33,34,38,39,42,43,44 and 45 will be D.D.R. outputs. Vdd3.3_2.5 should be connected to 2.5V for DDR power supply. When SEL_DDR is pulled low. Pin 4,5,6,7,10,11,15,16,19, 20,21 and 22 will be standard SDRAM outputs. Pin 27,28,29,30,33,34,38,39,42,43,44 and 45 will be DDR outputs, Vdd3.3_2.5 should be connected to 3.3V for SDRAM. SDATA * SCLK* Buffer_IN FB_output PD#* 24 25 13 1 36 I/O IN IN OUT IN Serial data of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd3.3_2.5 Serial clock of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd3.3_2.5 Reference input from chipset. 2.5V input for DDR only mode. 3.3V for standard SDRAM mode. Feedback clock for chipset. Output voltage depends on Vdd3.3_2.5 Active LOW input to enable Power Down mode and all outputs will be Three-Stated Internal pull-up resistor 120K to Vdd3.3_2.5 Clock outputs. Copies of Buffer_IN. Complementary copies of Buffer_IN Clock outputs. SEL_DDR=1, these pins are copies of Buffer_IN. SEL_DDR=0, these pins are copies of Buffer_IN. Voltage dpends on the Vdd3.3_2.5
DDR[6:11]T DDR[6:11]C DDR[0:5]T_SDRAM [0,2,4,6,8,10]
28,30,34,39,43, 45 27,29,33,38,42, 44 4,6,10,15,19, 21
OUT OUT OUT
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY
DDR[0:5]C_SDRAM [1,3,5,7,9,11] 5,7,11,16,20 22 OUT Clock outputs. SEL_DDR=1, these pins are complementary copies of Buffer_IN. SEL_DDR=0, these pins are copies of Buffer_IN. Voltage dpends on the Vdd3.3_2.5
4.5 Power Pins
SYMBOL Vdd3.3_2.5 Vdd2.5 Vss PIN 2,8,12,17,23 32,37,41,47 FUNCTION Connected to 2.5V when SEL_DDR=1 and 3.3V when SEL_DDR=0 Power supply 2.5V.
3,9,14,18,26,31,35, Ground 40,46
5.1 Register 6 : Control Register (default = 1)
Bit 7 6:5 4 3 2 1 0 @PowerUp 1 11 1 1 1 1 1 Pin 48 45,44 43,42 39,38 34,33 When the pin is low -level, Pin 27,28,29,30,32,33,34,,38,39,42,43 ,44,45 will be Three-Stated in the SDRAM Mode. DDR11T,DDR11C(Active / Inactive) DDR10T,DDR10C(Active / Inactive) DDR9T,DDR9C(Active / Inactive) DDR8T,DDR8C(Active / Inactive) Description SEL_DDR (Read back only) Reserved for winbond internal use, do not change them
5.2 Register 7: Control Register ( 1 = enable, 0 = Stopped )
Bit 7 6 5 4 3 2 @PowerUp 1 1 1 1 1 1 Pin 30,39 28,27 21,22 19,20 15,16 10,11 Description DDR7T,DDR7C(Active / Inactive) DDR6T,DDR6C(Active / Inactive) DDR5T_SDRAM10, DDR5C_SDRAM11(Active / Inactive) DDR4T_SDRAM8, DDR4C_SDRAM9 (Active / Inactive) DDR3T_SDRAM6, DDR3C_SDRAM7 (Active / Inactive) DDR2T_SDRAM4,
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY
DDR2C_SDRAM5 (Active / Inactive) 1 0 1 1 6,7 4,5 DDR1T_SDRAM2, DDR1C_SDRAM3 (Active / Inactive) DDR0T_SDRAM0, DDR0C_SDRAM1(Active / Inactive)
6. ACCESS INTERFACE
2 The W83196R-718 provides I C Serial Bus for microprocessor to read/write internal registers. In the W83196R-718 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2.
6.1 Block Write protocol
1 S 7 Slave Address 1 Wr 1 A 8 Command Code 1 A 8 Byte Count = N 1 A
8 Data Byte 1
1 A
8 Data Byte 2
1 A
8 Data Byte N
1 A
1 P
6.2 Block Read protocol
1 S 7 Slave Address 1 Wr 1 A 8 Command Code 1 A 1 Sr 7 Slave Address 1 Rd 1 A
8 Byte Count = N
1 A
8 Data Byte 1
1 A
8 Data Byte N
1 A 1
1 P
## In block mode, the command code must filled 8'h00
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY
6.3 Byte Write protocol
1 S 7 Slave Address 1 Wr 1 A 8 Command Code 1 A 8 Data Byte 1 A 1 P
6.4 Byte Read protocol
1 S 7 Slave Address 1 Wr 1 A 1 A 8 Command Code 8 Data Byte 1 A 1 A 1 P 1 S 7 Slave Address 1 Rd
6.5 The serial bus access timing
(a) Serial bus writes to internal address register followed by the data byte.
0 SCL SDA
Start By Master
7
8
0
7
8
1
0
1
1
0
0
1
R/W
0
Ack by Slave
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Slave
Frame 1 Serial Bus Address Byte
Frame 2 Internal Index Register Byte 7 8
SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
Ack by 784R Stop by Master
Frame 3 Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY
(b) Serial bus writes to internal address register only
0 SCL SDA
Start By Master
7
8
0
7
8
1
0
1
1
0
0
1
R/W
Ack by Slave
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Slave Stop by Master
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
Figure 2. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location.
0 SCL SDA
Start By Master
7
8
0
7
8
1
0
1
1
0
0
1
R/W
Ack by Slave
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Master Stop by Master
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
Figure 3. Serial Bus Read from Internal Address Register
(d) Serial bus read from a register with writing to internal address register.
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY
0 SCL SDA
Start By Master
7
8
0
7
8
...
1 0 1 1 0 0 1 R/W
Ack by Slave
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Slave
...
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
0 SCL SDA
7
8
0
7
8
... ...
Repeat Start By Master
1
0
1
1
0
0
1
R/W
Ack by Slave
D7
D6
D5
D4
D3
D2
D1
D0
Ack by Master Stop by Master
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
Figure 4. Serial Bus Read from Writing Internal Address Register
7.0
ORDERING INFORMATION
Part Number W83196R_718 Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
8.0
HOW TO READ THE TOP MARKING
W83196R-718 28051234 814GAB
1st line: Winbond logo and the type number: W83196R-196 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 Publication Release Date: July. 2002 Revision 1.0
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W83196R_718
PRELIMINARY
G: assembly house ID; O means OSE, G means GR A: Internal use code B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: July. 2002 Revision 1.0
W83196R_718
PRELIMINARY 9.0 PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2727 North First Street San Jose, California 95134 TEL: 1 -408-9436666 FAX: 1 -408-9436668
Taipei Office
9F, No. 480, Rueiguang Road, Neihu District, Taipei, 114, Taiwan TEL: 886-2-81777168 FAX: 886-2-87153579
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. Publication Release Date: July. 2002 Revision 1.0
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